As on-chip frequencies increase, there is a need to provide on-chip bypass capacitance to reduce the amount of noise current flowing through the power supply rails. The prior art analog macrocell uses accumulation-biased transistors for their high capacitance per unit area. Another prior art technique involves running supply rails on top of each other to get the benefit of the parasitic parallel plate capacitance. A recent paper, i.e., Fractal Capacitors, H. Samavati, et al., 1998 ISSCC, Session 16, TD: Advanced Radio-Frequency Circuits, Paper FP 16.6, 256-57, incorporated herein by reference, points out that sidewall or fringing capacitance yields a higher capacitance per unit area than conventional parallel plate capacitors as the distance between the plates decreases. The present invention is directed at using fringing capacitance to obtain increased capacitance on an integrated circuit in order to bypass supply lines with no resulting area penalty.